In an integrated circuit, a serial data receiver may be configured to operate at high speed, to achieve high data rate data transfers with other integrated circuits. In some embodiments the data rate and the corresponding clock rate may be sufficiently high that complementary metal oxide semiconductor (CMOS) circuits also within the integrated circuit may be incapable of operating at the same clock rate, or would exhibit unacceptably high power consumption were they operating at such a clock rate.
In such cases, a half-rate or quarter-rate decision feedback equalizer may be employed to convert the received serial data stream into two or four parallel data streams each at one half or one quarter, respectively, of the received data. Such a half-rate or quarter-rate decision feedback equalizer may be implemented in current mode logic, which, however, may exhibit relatively high power consumption.
Thus, there is a need for a low-power circuit for reducing the data rate of serial data.